The present invention relates generally to a semiconductor memory device and, more particularly, to a MIS (Metal-Insulator-Semiconductor) memory device of a one-transistor type.
In general, a MOS (broadly, MIS) memory device of a one-transistor type comprises a MOS transistor and in addition, a MOS capacitor. In this case, the transistor is used for charging or discharging the capacitor and the presence of charges in the capacitor corresponds to the information "0" or "1".
The above-mentioned transistor has a source (or drain) connected to a bit line, a gate connected to a word line and a drain (or source) connected to a first electrode of the capacitor which, in turn, has a second electrode connected to a power supply line.
According to a first conventional MOS memory device of a one-transistor type, the device is manufactured by using a so-called one-layer polycrystalline silicon technology. That is, the gate of the transistor and the second electrode of the capacitor are manufactured at the same time. However, in this device, an impurity doped region is required for connecting an inversion region (a channel region) of the transistor to an inversion region (the first electrode) of the capacitor. In addition, the field area thereof, which is explained below, is relatively large. As a result, the device is large and accordingly, the integrated density thereof is small.
According to a second conventional MOS memory device of a one-transistor type, the device is manufactured by using a so-called double-layer polycrystalline silicon technology. That is, the gate of the transistor is made of a first (lower) polycrystalline silicon layer, while the second electrode of the capacitor is made of a second (upper) polycrystalline silicon layer. In this device, the first and second polycrystalline silicon layers can be arranged so closely as to omit such an impurity region as mentioned in the first conventional device. In addition, the capacitor can be of a depletion type by using an E/D (enhancement/depletion) MOS manufacturing method, so that the charge storage of the capacitor can be increased. In other words, the capacitor can be of a small size. Therefore, the second conventional device is smaller than the first conventional device. However, the second conventional device is still relatively large.
According to a third conventional MOS memory device of a one-transistor type, the device is also manufactured by using a so-called double-layer polycrystalline silicon technology. However, the second electrode of the capacitor is made of the first polycrystalline silicon layer, while the gate of the transistor is made of the second polycrystalline silicon layer. In the third conventional device, active areas comprising impurity doped regions or the like can be interdigitally arranged so as to reduce the field area and accordingly, the area of the entire device. Therefore, a highly integrated density can be attained.
However, in the above-mentioned third conventional device, since the gate of the transistor is disposed partly on the second electrode of the capacitor, it is impossible to use an E/D MOS manufacturing method to the cell area, so that the capacitor is of an enhancement type. As a result, the charge storage of the capacitor is small; in other words, the capacitor is of a large size which enlarges the entire device. In addition, since the thickness of the insulating layer between the two polycrystalline silicon layers is small, the breakdown voltage of the insulating layer is low which invites a low reliability of operation and, in addition, the parasitic capacitance of each of the conductive layers is large which invites a low speed of operation.